1. Field of the Invention
The present invention relates to conductive bump structures and fabrication methods thereof, and more particularly, to a conductive bump structure on a substrate and a fabrication method thereof.
2. Description of Related Art
A flip-chip package is characterized in that a semiconductor chip is electrically connected to a packaging substrate through a plurality of solder bumps instead of using gold wires. In recent years, in order to meet the increasing demand for high-density, high-speed semiconductor elements and meet the miniaturization trend of electronic products, a flip-chip element are generally disposed on a organic circuit boards, for example, printed circuit boards, and an underfill is filled below the chips to reduce thermal stresses caused by different coefficient of thermal expansions (CIEs) of the silicon chips and the organic circuit boards.
Referring to FIG. 1A, a semiconductor chip 1 has a plurality of bonding pads 100 and a packaging substrate 4 has a plurality of conductive pads 40 corresponding to the bonding pads 100, respectively. By disposing a plurality of solder bumps 5 or other conductive adhesive material between the bonding pads 100 and the corresponding conductive pads 40, the semiconductor chip 1 is disposed on the packaging substrate 4 in a face-down manner. Therein, the solder bumps 5 or conductive adhesive material provides electrical I/O and mechanical connection between the semiconductor chip 1 and the packaging substrate 4.
In a conventional flip-chip process, a conductive bump 13 is formed on each of the bonding pads 100 of the semiconductor chip 1 (as shown in FIG. 1B) and a pre-solder bump (not shown) is formed on each of the conductive pads 40 of the packaging substrate 4 for facilitating alignment and connection between the semiconductor chip 1 and the packaging substrate 4. Then, the conductive bumps 13 are reflowed to the corresponding pre-solder bumps to form the solder bumps 5. Thereafter, referring to FIG. 1A, an underfill 6 is provided between the semiconductor chip 1 and the packaging substrate 4 to ensure the reliability of the electrical connection between the semiconductor chip 1 and the packaging substrate 4.
Referring to FIG. 1B, to fabricate the conductive bumps 13, a second insulating layer 12 is formed to cover a wafer 10 so as to protect the wafer 10 from being adversely affected by external environment, and the bonding pads 100 of the wafer 10 are exposed from the second insulating layer 12. Further, a first insulating layer 11 is formed on the second insulating layer 12 and a plurality of openings 110 are formed in the first insulating layer 11 for exposing the bonding pads 100, respectively. Then, a UBM (Under Bump Metallization) layer 131 is formed on the exposed bonding pads 100 and a solder material 134 is formed on the UBM layer 131 so as to form the conductive bumps 13. Subsequently, the wafer 10 is cut into a plurality of semiconductor chips 1 through a singulation process.
However, when reflowing the conductive bumps 13 made of the solder material 134, it is difficult to control the average value and deviation of the volume and height of the conductive bumps 13. If the average value of the volume of the conductive bumps 13 is relatively low such that the amount of the solder material is insufficient, the bonding pads 100 may be not wetted or only partially wetted by the solder material, thereby resulting in poor solder joints and reducing the reliability. On the other hand, if the average value of the volume of the conductive bumps 13 is relatively high such that the amount of the solder material is excessive, solder bridges can easily occur between adjacent solder joints.
Therefore, the deviation of the volume and height of the conductive bumps 13 is large, which not only can easily cause defects of the solder bumps 5 so as to lead to poor electrical connection, but also can easily result in poor coplanarity between the array-arranged solder bumps 5 so as to lead to poor solder joints and product failure. Therefore, the conductive bumps 13 made of the solder material 134 cannot meet the fine-pitch requirement of the semiconductor chip 1.
Accordingly, a flip-chip bump technique is provided. Referring to FIG. 1C, a copper post 132 is formed on the UBM layer 131 and a solder material 134 is further formed on the copper post 132. Since the reflow process does not change the shape of the copper post, the height and volume of the conductive bumps 13′ can be easily controlled so as to control the collapse range of the solder bumps 5. Therefore, the semiconductor chip 1 can easily meet the fine-pitch requirement.
However, along with the miniaturization of electronic products, I/O pitches and the size of the conductive bumps 13′ are decreasing. Since the copper post 132 has a rigid structure such that stresses of the rigid structure easily concentrate on an interface S between the UBM layer 131 and the first insulating layer 11, delamination can easily occur at the interface S, thus reducing the product reliability.
Therefore, there is a need to provide a conductive bump structure and a fabrication method thereof so as to overcome the above-described drawbacks.